This application claims the priority of Korean Patent Application No. 2004-5311, filed on Jan. 28, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to digital circuit technology, and more particularly, to a digital circuit that is tolerant of a race condition problem.
2. Description of the Related Art
A race condition is a problem that is caused in a digital circuit when there is a difference between a speed at which a signal input to a digital circuit is transmitted and a speed at which a signal enabling the digital circuit is transmitted. A dynamic multiplexer (MUX) is an example of a simple circuit for explaining the race condition problem.
FIG. 1 illustrates a conventional dynamic MUX. Referring to FIG. 5, a conventional dynamic MUX 100 includes a flip-flop (F/F) 110 operating in response to a clock signal CLK, a buffer 120 buffering the clock signal CLK, a MUX 130 transmitting an output data DATA of the F/F 110 in response to an output of the buffer 120, and a driver 140 outputting an output of the MUX 130 as an output signal OUT. The operation of the dynamic MUX 100 is determined by the MUX 130. A node signal E, i.e., the output of the buffer 120, enables the MUX 130 so that the output data DATA of the F/F 110 is transmitted to the driver 140.
FIG. 2 is a timing diagram that illustrates the operation of the dynamic MUX 100. The buffer 120 outputs the node signal E following a time delay in response to the clock signal CLK. The output data DATA of the F/F 110 is set to, for example, a logic “low” level. Taking into account the operation of the MUX 130, the output data DATA of the F/F 110 should be applied to the MUX 130 prior to the an enable signal, i.e., the node signal E.
However, as shown in FIG. 2, it may occur that the node signal E at a logic “high” level is generated prior to the output data DATA at the logic “low” level. In this case, the output signal OUT of the dynamic MUX 100 is at the logic “low” level when the node signal E is activated and then becomes the desirable logic “high” level in response to the output data DATA of the F/F 110. In other words, when the output data DATA of the F/F 110 is applied at a time that is later than the node signal E, the dynamic MUX 100 does not output a desired signal when the node signal E, the enable signal, is activated. A difference between a time when the output data DATA of the F/F 110 is applied to the MUX 130 and a time when the node signal E is applied to the MUX 130 becomes a racing condition problem, which causes the dynamic MUX 100 to operate unreliably.